This invention relates to an electrical circuit (e.g., CMOS LSI) formed by elements and signal lines. More particularly, it pertains to a method and apparatus for estimation of power dissipation in an electric circuit, and to a method and apparatus of determining a layout of circuit components and interconnection routing of signal lines to connect together the circuit components (hereinafter called the layout/routing plan).
As the density of SIC (semiconductor integrated circuit) increases, the number of elements forming a circuit increases. Therefore, a way off arranging a great number of elements and providing adequate interconnecting routing to them has been considered very important. Suppose two different circuits. These two circuits employ the same number of elements interconnected together with the same number of signal lines, but they are formed using different layout/routing plans. In such a case, there might be a difference in the power dissipation between the two circuits. Greater power dissipation results in power loss and presents the problem that a way of releasing developed heat to outside the circuit must be found.
If exact pre-estimation of power dissipation in an electric circuit is possible, then, based on this estimation, an optimum layout/routing plan can be designed with ease. For example, a way of pre-estimating power dissipation is shown in "VLSI Design I," the Iwanami Koza Microelectronics Series, published by IWANAMI SHOTEN. In this approach, a signal line, which establishes connections among many points in a circuit, is measured to find its approximate virtual wiring length. Based on the found virtual wiring length, an evaluating function is set, and an iterative improvement method is used to minimize an objective function. In other words, if the cross-sectional area of a wire is almost constant, then the wire load is directly proportional to the wiring length. As a result, those such as the power dissipation and the signal delay can synthetically be evaluated from the virtual wiring length.
Japanese Patent Application, published under Pub. No. 2-171861, discloses another technique. In accordance with this technique, an electrical circuit is assigned a predetermined test pattern. The number of times each signal line of the electrical circuit makes a switch is found by means of, for example, a logical simulator. The result found is then multiplied by a wiring capacitance of each signal line. The products found are summed together to estimate power dissipation in the circuit.
The former technique considers only the approximate virtual wiring length. This produces the problem that exact estimation of power dissipation is difficult to find. The reason is explained by taking, for example, two different circuits having the same total wiring length. In this case, if one of the two circuits switches more times than the other circuit then it will dissipate more power than the other circuit. Accordingly, estimating power dissipation by considering only the wiring length may cause serious error.
The latter technique is a technique that makes use of the fact that a very large current flows when a signal is changing. The number of times such a signal change is made is considered, which enhances the power dissipation estimation accuracy. However, execution of logical simulations requires an appropriate test pattern, and preparing such a test pattern is very time consuming. Further, execution of logical simulations itself is also very time consuming.